User:ZyMOS/temp/chip carrier

This page contains all computer chip or integrated circuit packages. A chip package is what surrounds the integrated circuit die and connects the die's pads to the packages external pins.

=Types of Leads/Contacts=
 * J-Lead
 * Gull-wing Lead
 * C-Bend Lead
 * I-Lead
 * Bat-wing Lead
 * Through-Hole Lead
 * Exposed Pad
 * Ball (solder ball)
 * Tab (Heatsink)
 * Land pad (Non-leaded/No-lead)
 * Pin
 * Column

=Standard Packages=
 * Commonly used packages
 * PGA: Pin grid array
 * DIP: Dual in-line package
 * BGA : Ball grid array
 * SO: Small outline
 * SOIC: Small outline intergrated circuit
 * SOP: Small outline package
 * SOT: Small outline transistor
 * QFP: Quad flat package
 * LCC: Leaded chip carrier
 * TO: transistor outline


 * Less Common


 * Uncommon

=Chip packages=


 * In-line packages
 * DIP
 * SIP
 * ZIP


 * Optical packages
 * Photodiode
 * LED
 * IR


 * Pin grid array


 * Small outline package:
 * SO
 * SOP
 * SOIC
 * SOT
 * SC


 * User:ZyMOS/temp/chip_carrier/Diode and transistor outline
 * TO
 * DO


 * User:ZyMOS/temp/chip_carrier/Ball grid array
 * BGA
 * CSP
 * Micro-array
 * MicroSMD
 * CGA: Column grid array


 * User:ZyMOS/temp/chip_carrier/quad package
 * QFP


 * User:ZyMOS/temp/chip_carrier/leadless package
 * QFN
 * SON
 * LGA


 * User:ZyMOS/temp/chip_carrier/J-lead package
 * SOJ
 * LCC


 * 2 lead package
 * Diodes
 * Resistors
 * Capacitors
 * inductors


 * I-lead package
 * CERPACK
 * CERQUAD
 * QFI
 * SOI


 * Non-standard


 * Unsorted

=Chip Carrier Related Acronyms=
 * Chip-on-Lead (COL
 * Top Exposed Pad (TEP)
 * EP, EXP: Exposed pad
 * L, LD: Lead
 * SiP: System in Package
 * JEDEC: Joint Electron Device Engineering Council
 * JEITA: Japan Electronics and Information Technology Industries Association
 * SoC: System on Chip
 * Pb: lead
 * Sn: tin
 * Cu: Copper
 * Ag: Gold
 * EIA: Electronic Industries Alliance
 * MCP: Milti-Chip Package
 * EIAJ: Electronic Industries Association of Japan
 * TAB: Tape Automated Bonding

=See Also=
 * Guide to computer chip or integrated circuit identification

=External Links=
 * JEITA package standards downloads
 * http://www.standardics.nxp.com/packaging/package.outlines/
 * http://www.nxp.com/package/
 * http://www.analog.com/Analog_Root/Packages/Packages_Home/0,2299,1,00.html
 * *http://www.amkor.com/products/productfamilies.cfm


 * http://acronyms.thefreedictionary.com/

=New links=
 * http://www.talkingelectronics.com/projects/CircuitTricks/CircuitTricks-1.html
 * GOOD: http://icmaster.co.kr/Semi/hitachi/pdf/pkg.pdf
 * GOOD: http://ww1.microchip.com/downloads/en/EnvironmentalInformation/en026304.pdf
 * http://sti-lt.ac-rouen.fr/Microtechniques/BTS_CIM/Articles/Doc%20Microship.pdf
 * ALL ee words: http://cpu.linuxmania.net/liste/cpuinfo/chip-abbreviations.htm
 * http://productsearch.machinedesign.com/Specifications/Semiconductors/Discrete/Thyristors/Silicon_Controlled_Rectifiers_SCR

=completed=
 * http://www.analog.com/Analog_Root/Packages/Packages_Home/0,2299,1,00.html
 * http://www.amkor.com/products/productfamilies.cfm
 * http://www.fairchildsemi.com/packaging/