| Line 19: | Line 19: | ||
| [[Image:Ic leads-through-hole.png|thumb|none|100px|DIP Through-Hole ]] |
| [[Image:Ic leads-through-hole.png|thumb|none|100px|DIP Through-Hole ]] |
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|- |
|- |
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| + | | [[Image:Ic_leads-exposed_pad.png|thumb|none|100px|Exposed Pad]] |
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| − | | Exposed Pad |
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| [[Image:Ic leads-solder ball.png|thumb|none|100px|Ball (solder ball)]] |
| [[Image:Ic leads-solder ball.png|thumb|none|100px|Ball (solder ball)]] |
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| [[Image:Ic leads-Heat-tab.jpg|thumb|none|100px|Tab (Heatsink)]] |
| [[Image:Ic leads-Heat-tab.jpg|thumb|none|100px|Tab (Heatsink)]] |
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Revision as of 17:45, 23 October 2007
A chip package is what surrounds the integrated circuit die and connects the die's pads to the packages external pins. They are often a chip carriers, or IC packages.
Types of Leads/Contacts
The pieces of metal that electrically connect the IC to a circuit board are called leads.
 J-Lead |
 Gull-wing |
 C-Bend |
  I-Lead |
  Bat-wing |
  DIP Through-Hole |
  Exposed Pad |
  Ball (solder ball) |
  Tab (Heatsink) |
  Land pad (Non-leaded/No-lead) |
PGA Pin | Column |
Common Packages
- CPGA: Ceramic pin grid array
- PDIP: Plastic dual in-line package
- BGA : Ball grid array
- SO: Small outline
- SOIC: Small outline integrated circuit
- SOT: Small outline transistor
- PQFP: Plastic quad flat package
- PLCC: plastic leaded chip carrier
- TO: transistor outline
Chip packages
- In-line package
- DIP
- SIP
- ZIP
- Optical package
- Photodiode
- LED
- IR
- Photo interrupt
- Pin grid array
- PGA
- Small outline package:
- SO
- SOP
- SOIC
- SOT
- SC
- Ball grid array
- BGA
- CSP
- Micro-array
- MicroSMD
- CGA: Column grid array
- Quad package
- QFP
- HQFP
- Leadless package
- QFN
- SON
- LGA
- J-lead package
- SOJ
- LCC
- 2 lead package
- Diodes
- DO
- SOD
- Resistors
- Capacitors
- inductors
- Diodes
- I-lead package
- CERPACK
- CERQUAD
- QFI
- SOI
See all chip package images: Category:Chip package image
Chip Carrier Related Acronyms
- COL: Chip-on-Lead
- TEP: Top Exposed Pad
- EP, EXP: Exposed pad
- L, LD: Lead
- SiP: System in Package
- JEDEC: Joint Electron Device Engineering Council
- JEITA: Japan Electronics and Information Technology Industries Association
- SoC: System on Chip
- ASIC: Application specific Integrated circuit
- Pb: lead
- Sn: tin
- Cu: Copper
- Ag: Gold
- EIA: Electronic Industries Alliance
- MCP: Mult-Chip Package
- EIAJ: Electronic Industries Association of Japan
- TAB: Tape Automated Bonding
See Also
External Links
- JEITA package standards downloads
- http://www.standardics.nxp.com/packaging/package.outlines/
- http://www.nxp.com/package/
- http://www.analog.com/Analog_Root/Packages/Packages_Home/0,2299,1,00.html
- *http://www.amkor.com/products/productfamilies.cfm
New links
- http://www.talkingelectronics.com/projects/CircuitTricks/CircuitTricks-1.html
- GOOD: http://icmaster.co.kr/Semi/hitachi/pdf/pkg.pdf
- GOOD: http://ww1.microchip.com/downloads/en/EnvironmentalInformation/en026304.pdf
- http://sti-lt.ac-rouen.fr/Microtechniques/BTS_CIM/Articles/Doc%20Microship.pdf
- ALL ee words: http://cpu.linuxmania.net/liste/cpuinfo/chip-abbreviations.htm
- http://productsearch.machinedesign.com/Specifications/Semiconductors/Discrete/Thyristors/Silicon_Controlled_Rectifiers_SCR
- NEC
- Intersil
- ROHM
- Sony
- TI
- http://www.pcmag.com/encyclopedia_term/0,2542,t=chip+package&i=39645,00.asp
- SMD components
- http://www.fpga-guide.com/package/package.html
- SMD Dictionary
- BGA Packages
- http://www.2ic.cn/bbs/viewthread.php?tid=287902
- http://www.upv.es/amiga/198.htm (Spanish)
- BGA side profiles
- BGA side profiles
- BGA side profiles